Since the introduction of the flip chip technology by IBM in the early 1960s, the flip chip devices have been mounted on an expensive ceramic substrate where the thermal expansion mismatch between the silicon chip and the ceramic substrate is less critical. In comparison with wire bonding technology, the flip chip technology is better able to offer higher packaging density (lower device profile) and higher electrical performance (shorter possible leads and lower inductance). On this basis, the flip chip technology has been industrially practiced for the past 40 years using high-temperature solder (controlled-collapse chip connection, C4) on ceramic substrates. However, in recent years, driven by the demand of high-density, high-speed and low-cost semiconductor devices for the trend of miniaturization of modern electronic products, the flip chip devices mounted on a low-cost organic circuit board (e.g. printed circuit board or substrate) with an epoxy underfill to mitigate the thermal stress induced by the thermal expansion mismatch between the silicon chip and organic board structure have experienced an explosive growth. This notable advent of low-temperature flip chip joints and organic-based circuit board has enabled the current industry to obtain inexpensive solutions for fabrication of flip chip devices.
In the current low-cost flip chip technology, the top surface of the semiconductor integrated circuit (IC) chip has an array of electrical contact pads. The organic circuit board has also a corresponding grid of contacts. The low-temperature solder bumps or other conductive adhesive material are placed and properly aligned in between the chip and the circuit board. The chip is flipped upside down and mounted on the circuit board, in which the solder bumps or conductive adhesive materials provide electrical input/output (I/O) and mechanical interconnects between the chip and circuit board. For solder bump joints, an organic underfill encapsulant may be further dispensed into the gap between the chip and circuit board to constrain the thermal mismatch and lower the stress on the solder joints.
In general, for achieving a flip chip assembly by solder joints, the metal bumps, such as solder bumps, gold bumps or copper bumps, are commonly pre-formed on the pad electrode surface of the chip, in which the bumps can be any shape, such as stud bumps, ball bumps, columnar bumps, or others. The corresponding solder bumps (or say presolder bumps), typically using a low-temperature solder, are also formed on the contact areas of the circuit board. At a reflow temperature, the chip is bonded to the circuit board by means of the solder joints. After dispensing of an underfill encapsulant, the flip chip device is thus constructed. Such methods are well known in the art and typical examples of the flip chip devices using solder joints are for example described in U.S. Pat. No. 7,098,126 (H. -K. Hsieh et al.).
Currently, the most common method for formation of presolder bumps on the circuit board is the stencil printing method. Some prior proposals in relation to the stencil printing method can be referred to U.S. Pat. No. 5,203,075 (C. G. Angulas et al.), U.S. Pat. No. 5,492,266 (K. G. Hoebener et al.) and U.S. Pat. No. 5,828,128 (Y. Higashiguchi et al.). Solder bumping technique for flip chip assemblies requires design considerations regarding both bump pitch and size miniaturization. According to practical experiences, the stencil printing will become infeasible once the bump pitch is decreased below 0.15 millimeter. In contrast, the solder bumps deposited by electroplating offer the ability to further reduce bump pitch down to below 0.15 millimeter. The prior proposals in relation to electroplate bumps on the circuit board for flip chip bonding can be found in U.S. Pat. No. 5,391,514 (T. P. Gall et al.) and U.S. Pat. No. 5,480,835 (K. G. Hoebener et al.). Although electroplate solder bumping on the circuit board offers finer bump pitch over stencil printing, it presents several challenges for initial implementation.
A multi-step process to form solder on an organic substrate is described in U.S. Pat. No. 7,098,126 (H. -K. Hsieh et al.). In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact area. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by electroplating. Finally, the resist and the metal seed layer beneath the resist are removed. To apply this method various patterning steps are required which is not desired from the overall standpoint of process efficiency. Furthermore the method has its limitations if the distance between adjacent contact areas (pitch) is very small as a result of the miniaturization of electronic devices.
A method for forming metal bumps is disclosed in US 2007/0218676 A1. The method disclosed therein comprises application and planarization of a first photo resist prior to deposition of a conductive layer and requires a patterned photo resist to remove excess solder material and parts of the conductive layer.
A conventional process to form void free BGA (Ball Grid Array) solder joints, e.g., between a printed circuit board and an IC substrate is shown in FIG. 1. A substrate 103a, 103b having blind micro vias (BMV's) 104 exposing inner contact pads 102 is coated with a solder resist layer 112. The solder resist layer 112 is structured to form solder resist openings (SRO's) 113. Next, the BMV's 104 are conformally coated with a metal layer 115, e.g., a copper layer. Solder balls 117 are attached to the SROs (FIG. 1b), a second substrate 116 having outer layer contact pads 120 is mounted onto the substrate having solder balls 117 attached and subjected to a reflow process. During reflow the solder balls 117 then become solder joints 118. Voids 119 are formed inside the solder joints 118 and BMV's 104 which reduce the mechanical stability and electrical conductivity of solder joints 118 and are therefore not desired.
Instead of solder balls 117 known processes also use screen printed solder paste. However, formation of voids 119 occurs also in this case.
The formation of voids 119 is especially an unsolved problem for BMV's having a diameter of less than 200 μm.